IBM has unveiled the prototype of a chip capable of reducing energy usage by up to 85%, featuring a design that allows transistors to be stacked vertically on the surface of the chip.
Developed in partnership with Samsung Electronics at IBM's Albany, N.Y., Nanotech Center, IBM plans to use the processor not just in its server-based systems, where it can reduce the energy requirements for cryptomining operations and data encryption tasks, but in a range of consumer devices, including cell phones that could hold a charge for a week.
For instance, IBM believes there is a significant opportunity for the new chips among IoT and edge devices where its energy-saving properties could be useful because energy sources are not available, such as ocean buoys, autonomous vehicles and spacecrafts.
One analyst said he believes the upcoming technology holds promise for users to improve their mobile and edge technologies by putting more reliable systems and devices in place.
"As edge strategies start to take hold, how we get connected and stay connected for meaningful amounts of time or improve the compute power of remote systems for AI grows in importance," said Dan Newman, founding partner and principal analyst of Futurum Research. "Announcements like this from an IBM or Arm looking to solve difficult problems like this is an important development."
Vertical CPU transistor stacking benefits
The ability to stack transistors vertically instead of laying them flat on the surface of the chip not only allows vendors to pack many more transistors on a chip but is also the primary reason the upcoming chip design is significantly more energy-efficient.
Both chipmakers and corporate users can benefit from the new design because it gives them a way of getting around the constraints of Moore's Law, the principle laid down by Intel's Gordon Moore in 1965 that states there would be a doubling of the number of transistors on a microchip every two years, later revised to every 18 months. But over the past several years chipmakers have begun to run out of "real estate" on CPUs to cram in any more transistors.
The new technology centers around IBM's Vertical Transport Field Effect Transistors (VTFET) allowing transistors to be implemented perpendicular to the surface of the chip, enabling an up-and-down electrical current flow. This allows for greater current flow and eliminates wasting energy, IBM said.
The new chip represents IBM's attempts to "challenge convention and rethink how the chip industry can improve business and reduce environmental impact," said Mukesh Khare, vice president of hybrid cloud and systems at IBM Research, in a statement.
IBM will have a couple formidable competitors in this market, as both Intel and Taiwan Semiconductor Manufacturing Company (TSCM) plan to have new chip designs out in the 2023-2024 timeframe.
Earlier this month, Intel said it is investing significant research into scaling technologies for delivering more transistors, but is taking a different approach from IBM. Company researchers outlined solutions for the design, process and assembly challenges of hybrid bonding interconnect. They believe this approach will result in more than a tenfold interconnect density improvement in terms of packaging.
At it its Accelerated conference in July, Intel said it plans to introduce Foveros Direct, enabling sub-10-micron bump pitches. This capability would provide an order of magnitude increase in the interconnect density for 3D stacking. This in turn permits the ecosystem to gain benefits of advanced packaging.
IBM, meanwhile, believes its new design can aid CPU developers in creating a new device architecture that would accelerate semiconductor device scaling beyond nanosheet.
Frank DzubeckPresident, Communications Network Architects, Inc.
The upcoming chips, which are expected to be available sometime in 2024, will be used in IBM's future Power servers as well as their Z series of mainframes. Samsung also manufactures the seven-nanometer chips in IBM's Power 10 servers along with the IBM Telum processor unveiled earlier this year, which are both based on IBM designs.
"IBM can take this technology in a couple of directions," said Frank Dzubeck, president of Communications Network Architects, Inc. "They can extend it for use internally with their Power series and mainframes, but also license it externally to a variety of companies working both in the high-tech and consumer markets."
The new technology also benefits IBM's manufacturing processes for future two-nanometer, one-nanometer and sub-one-nanometer chips, which could keep them competitive over the next few years with Intel, Arm and TSCM.
"This new technology looks like a modification of the same technology IBM will use in producing one-nanometer chips, except you can stack [transistors] vertically," Dzubeck said. "And with this level of energy savings, their water-cooled mainframes may not need water, which cuts down on costs."
As editor at large with TechTarget's news group, Ed Scannell is responsible for writing and reporting breaking news, news analysis and features focused on technology issues and trends affecting corporate IT professionals. He has also worked for 26 years at Infoworld and Computerworld covering enterprise-class products and technologies from larger IT companies including IBM and Microsoft, as well as serving as the editor of Redmond for three years, overseeing that magazine's editorial content.