multi-level cell (MLC)

What's the difference between enterprise MLC and consumer MLC?

Multi-level cell flash is a midpoint between single-level cell (SLC) and triple-level cell (TLC) flash memory. NAND flash has a finite number of write cycles. Because multi-level cell flash generally is less expensive than SLC, it is the preferred solid-state storage memory of manufacturers of consumer-based electronic devices.

Enterprise multi-level cell (eMLC) drives are designed with an enhanced form of multi-level cell flash that can accommodate a larger number of write cycles. Various techniques are used to enable eMLC to be used to design inexpensive enterprise solid-state drives (SSDs). These techniques include algorithms to boost the unrecoverable bit-error rate, flash overprovisioning, wear leveling and write amplification. Most of these techniques are enabled by software.

Consumer-grade MLC flash provides a program-erase cycle of 3,000 to 10,000 writes, compared to a 20,000 to 30,000 endurance level of eMLC.

How multi-level cell flash compares to single-level cell flash

One of the drawbacks of multi-level cell flash is its higher bit rate when compared to single-level cell NAND flash. The more bits a cell contains, the fewer write cycles it can accommodate and the greater the chance that errors will occur.

Single-level cell flash uses a high grade of NAND memory, storing 1 bit per cell and always in one of two voltage states: programmed, denoted as 0, or erased, denoted as 1. Having only two states means data in single-level cell flash enables data to be interpreted quickly and reduces bit errors. However, since SLC flash stores fewer data bits per cell, it generally is considered a more costly form of storage memory than multi-level cell flash.

Multi-level cell flash's potential for multiple voltage states decreases its manufacturing costs and has led to widespread use of the technology in cellphones, digital cameras, handheld music players and USB flash drives.

MLC flash memory cards typically deliver a slower transfer speed and consume more power. A multi-level cell is divided into four states, designated by the level of electrical charge applied to the cell. MLC has two states, MLC-3 has eight states and MLC-4 has 16 states.

Allowing multiple electrical states also can result in higher error rates with multi-level cell flash.

Upon reaching its write limit, a NAND flash cell will start to fail, which can corrupt data. To compensate, vendors have tried to address the problem by devising smarter flash controllers.

Triple-level cell: Successor to consumer flash?

Triple-level cell flash pushes the boundaries of NAND flash. As the name suggests, triple-level cell NAND stores three bits of data per flash media. Triple-level cell NAND makes use of advances in semiconductor process geometries to offer higher densities than planar NAND.

The drawback of triple-level cell flash stems from the higher error correction needed to decipher the signal crosstalk that results from storing more bits per cell. To date, triple-level cell SSDs have made only limited appearances as an enterprise flash technology, mostly to serve high-volume reads. Dell EMC SC Series hybrid arrays and Kaminario all-flash arrays are among the early vendor products to incorporate TLC NAND-based SSDs.

Flash vendors push boundaries of NAND

Leading flash vendors are pushing the boundaries of multi-level cell flash. 3D NAND flash memory is a newer architecture for designing flash chips. In 3D NAND, manufacturers stack multiple layers of memory cells in a vertical layout. The stacking method reduces electrical interference that occurs when cell sizes are shrunk. Leading producers of 3D NAND flash include Intel Corp. (in partnership with Micron Technology), Samsung, SK Hynix Inc. and Western Digital Corp., which has been a partner with Toshiba. The future of the Toshiba-Western Digital partnership is unclear due to a dispute with Western Digital subsidiary SanDisk, which is contending a proposed sale of Toshiba to a consortium comprising Apple Corp., Dell Technologies Capital, Kingston Technology Corp. and Seagate Technology.

Samsung has disclosed preliminary design for quad-level cell flash, based on a 64-layer 3D NAND design architecture. In July 2017, Western Digital previewed the 64-layer X4 NAND architecture for multi-level cell flash, as well as its 96-layer BiCS4 vertical NAND technology.