What is Scalable Processor Architecture (SPARC)?
Scalable Processor Architecture (SPARC) is a 32- and 64-bit microprocessor architecture developed by Sun Microsystems in 1987. SPARC is based on reduced instruction set computing (RISC). SPARC has become a widely used architecture for hardware used with UNIX-based operating systems, including Sun's own Solaris systems. Sun made SPARC an open architecture that is available for licensing to microprocessor manufacturers.
Sun was acquired by Oracle Corporation in January 2010.
With its highly scalable open architecture, SPARC is aimed at optimizing compilers and creating effective pipelines for hardware executions. SPARC implementations have also led to high execution rates and relatively short time-to-market development schedules. In addition, SPARC can be scaled up or down to substantially minimize interference and context switching time.
History of SPARC
The development of SPARC and its later versions, MicroSPARC and UltraSPARC, were the result of more than two decades of technical research and innovation. Here's a quick rundown on the SPARC development timeline:
- 1984 - SPARC development begins
- 1986 - Sun's first SPARC processor, the SPARC V7, is introduced
- 1987 - Sun ships first the SPARC workstation
- 1989 - SPARC International is founded with the open SPARC instruction set architecture (ISA)
- 1992 - Sun introduces 32-bit SPARC V8
- 1992 - MicroSPARC introduced
- 1993 - Sun introduces 64-bit (address + data) SPARC V9
- 1994 - MicroSPARC discontinued
- 1995 - Sun ships UltraSPARC I, Sun's first 64-bit core
- 1997 - UltraSPARC II ships
- 2001 - UltraSPARC III ships
- 2004 - Sun ships UltraSPARC IV dual-core with basic chip multithreading (CMT)
- 2005 - UltraSPARC T1, the first 8-core CMT processor, ships
- 2007 - UltraSPARC Architecture 2007 is released with UltraSPARC T2
- 2010 - Oracle Corporation acquires Sun Microsystems
- 2012 - Oracle SPARC Architecture 2011 is released with visual instruction set 3 extensions (VIS 3) and hyperprivileged mode
- 2015 - Oracle releases SPARC M7 based on the Oracle SPARC Architecture 2015 with VIS 4 extensions and hardware-assisted encryption
- 2017 - SPARC M8 released
SPARC architecture characteristics and components
SPARC features a load and store architecture wherein operations are done over registers. It uses a register window concept with a large number of registers and delay slots to optimize branch instruction. It also passes arguments using these registers and the stack.
The SPARC architecture is characterized by the following:
- reduces the number of instructions the processor has to perform;
- reduces the number of types of memory addresses the processor needs to handle;
- puts very little processor operation in microcode, which requires clock speed-consuming time to access; and
- provides language compilers that are optimized for a SPARC microprocessor.
The SPARC architecture consists of these components:
- Integer unit (IU). The IU consists of general-purpose, 64-bit registers that control the overall operation of the processor. It can include 64 to 528 registers that are partitioned into eight global registers, eight alternate global registers and register windows in a circular stack of three to 32 sets of 16 registers each. The IU executes integer arithmetic instructions and computes memory addresses for loads and stores. It also controls instruction execution for the floating-point unit and maintains program counters.
- Register window. An instruction can access the eight global registers and a 24-register window at any given time. One register window consists of 16 registers divided into eight in registers and eight local registers. It also includes the eight in registers of an adjacent register set that are addressable as its eight out registers from the current window. In the input registers, arguments are passed to a function, while local registers are used to store local data, and output registers are where the programmer puts the arguments when calling a function.
- Floating-point unit (FPU). The FPU contains 32 32-bit floating-point registers (single precision), 32 64-bit floating-point registers (double precision) and 16 128-bit floating-point registers (quad precision). The double-precision values occupy an odd-even pair of single-precision registers, while the quad precision values occupy an even-odd pair of double-precision registers. The floating-point load/store instructions are used to move data between the memory and FPU. The floating-point arithmetic operations and comparisons are performed using floating-point operate (FPop).
- Coprocessor unit (CU). The support for a single, implementation-dependent coprocessor is included in the instruction set. The coprocessor load/store instructions, which are mirrored by floating-point instructions, move data between the registers and memory.
Benefits and advantages of SPARC
SPARC's design and architecture offer many benefits. They are as follows:
- SPARC is highly scalable and open source, providing license flexibility and the opportunity for users to configure their own new solutions using the SPARC architecture.
- SPARC paves the way for a higher number of disentangled instruction sets with fewer transistors.
- The SPARC structure is scalable and adaptable, both in terms of cost and capacity.
- The architecture is fully compatible across generations with backward binary compatibility.
- It is versatile, with numerous possibilities for commercial, aerospace, military and technical applications.
- SPARC incorporates object-oriented programming (OOP) features.
SPARC also offers the following advantages:
- simple, straightforward and powerful architecture;
- easy adaptability to meet real-world expectations and applications;
- higher scalability and accessibility;
- lowers total cost of ownership and increases per-center productivity; and
- SPARC V9 structure decreases CPU wait time and improves CPU usage time.